As integrated circuit memory devices become more highly integrated and complex, the operational speed of the device may be increased. As the capacity of the memory increases the propagation delays of signals therein may become a significant portion of timing in the memory. Specifically, the propagation delay of input signals (e.g., an address signal) used to drive a decoder may be an issue as the input signals may be relatively far from the decoder.
In addition, word lines connected to the gates of cell transistors may be formed of poly silicon, which may have a large resistivity. Also, since the word lines may pass above a gate oxide layer of the cell transistor, the capacitance C may be significant, which may increase an associated RC delay as the length of the word line increases. To compensate for the increased RC delay of the word line, the word line voltage may be increased, which may also increase the area occupied by a row decoder. Furthermore, if the bit line becomes long, the resistance R and capacitance C associated therewith may also be increased, which may also increase an area of the row decoder.
Since the word lines and the bit lines are long-distance interconnects, the propagation delay of each may be long. Furthermore, the size of the decoder may also increase as a memory block size is increased, which may also increase delay time due to, for example, increased decoding time.
It is known to divide memory banks into memory blocks (e.g., four memory blocks), and a decoder is used for each memory block in the bank. This approach has been used due to some of the advantages of this approach, such as operational speed. However, this approach also offers some disadvantages, such as power consumption. However, there are advantages in aspect of operation speed or power consumption, so that this manner has been widely used recently.
FIG. 1 is a block diagram showing a conventional memory partitioning approach including input signals. It will be understood that the arrangement of only one memory bank is discussed below, however, the arrangements in the remaining memory banks are analogous to the arrangement discussed. As shown in FIG. 1, a memory cell array can be divided into two memory banks 100, 200. Each of the memory banks (e.g., 100 in FIG. 1) is divided into four memory blocks 110, 120, 130 and 140. Decoders 150, 160, 170 and 180 are located between each memory block. The memory banks 100, 200 are arranged in a matrix shape.
A signal generator 600 generates address signals for selecting a specific address in a memory block, which is input to the decoder. In particular, the address signal shown selects memory blocks 110, 210, 310 and 410, which are located in each of the memory banks 100, 200, 300 and 400. The difference in the lengths of the lines which carry the address signal to the different memory blocks may cause an access in each of the memory blocks 110, 210, 310 and 410 in the separate memory banks to occur at slightly different times. However, if the size of the memory blocks A, B, C, and D becomes too large, and the decoder becomes too long, the distance that a address signal may have to propagate may become so long that a difference in phase may be introduced between the signals in the different memory blocks. For example, the time for driving the A blocks 110 and 310 may be longer than the time for driving the A blocks 210 and 410 as the address signal must travel farther to reach the A blocks 110 and 310. Additionally, if the decoder becomes to long, an address signal may be is incapable of full swing so that a high frequency characteristic may be reduced. In addition, the rising/falling time may depend on position of the block.